NB3N121KMNG - 

The NB3N121K is a differential 1:21 Clock and Data fanout buffer with High-speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N121K is designed with HCSL PCI Express clock distribution and FBDIMM applications in mind. Inputs can directly accept differential LVPECL, HCSL, and LVDS signals Single ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply Input pins incorporate separate internal 50 Ω termination resistors allowing additional single ended system interconnect flexibility. Output drive current is set by connecting a 475 Ω resistor from IREF to GND. Outputs can also interface to LVDS receivers when terminated. The NB3N121K specifically guarantees low output–to–output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB3N121K's performance to distribute low skew clocks across the backplane or the motherboard.

Features:

Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and 400 MHz

340 ps Typical Rise and Fall Times

800 ps Typical Propagation Delay

100 ps Max Within Device Skew

150 ps Max Device-to-Device Skew

tpd 100 ps Maximum Propagation Delay Variation Per Each Differential Pair

0.1 ps Typical RMS Additive Phase Jitter

LVDS Output Levels Optional with Interface Termination

Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V

Typical HCSL Output Level (700 mV Peak-to-Peak)

These are Pb-Free Devices Applications

Clock Distribution

PCIe I, II, III

Networking

High End Computing

Routers

End Products:

Servers

FBDIMM Memory Card